Генератор Verilog для индексных умножителей по модулю (Модуль: 11)

Генератор Verilog для индексных умножителей по модулю

Первообразный корень для 11 = 2
Число P-1 может быть разложено на 2 взаимнопростых множителя: 10 = 2*5
Таблица преобразования [Подробности]:

1	2	3	4	5	6	7	8	9	10
0	1	8	2	4	9	7	3	6	5
( 0 0 )	( 1 1 )	( 0 3 )	( 0 2 )	( 0 4 )	( 1 4 )	( 1 2 )	( 1 3 )	( 0 1 )	( 1 0 )

module multiplication_mod_11(inp1, inp2, out);
	input [3:0] inp1;
	input [3:0] inp2;
	output reg [3:0] out;
	wire [3:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [2:0] w_1_1;
	wire [2:0] w_2_1;
	wire [2:0] wout_1;
	lut_input_11 lut1(inp1, w_1_0, w_1_1);
	lut_input_11 lut2(inp2, w_2_0, w_2_1);
	sum_modulo_2 sm0(w_1_0, w_2_0, wout_0);
	sum_modulo_5 sm1(w_1_1, w_2_1, wout_1);
	lut_output_11 lut3(wout_0, wout_1, out_pre);
	always @ (*)
	begin
		if (inp1 == 0 || inp2 == 0)
		begin
			out = 0;
		end
		else
		begin
			out = out_pre;
		end
	end
endmodule

module sum_modulo_2(inp1, inp2, out);
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 2)
		begin
			out = int;
		end
		else
		begin
			out = int - 2;
		end
	end
endmodule

module sum_modulo_5(inp1, inp2, out);
	input [2:0] inp1;
	input [2:0] inp2;
	output reg [2:0] out;
	wire [3:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 5)
		begin
			out = int;
		end
		else
		begin
			out = int - 5;
		end
	end
endmodule

module lut_output_11(inp0, inp1, out);
	output reg [3:0] out;
	input [1:0] inp0;
	input [2:0] inp1;
	always @ (*)
	begin
		if (inp0 == 0 && inp1 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 1 && inp1 == 1)
		begin
			out <= 2;
		end
		else if (inp0 == 0 && inp1 == 3)
		begin
			out <= 3;
		end
		else if (inp0 == 0 && inp1 == 2)
		begin
			out <= 4;
		end
		else if (inp0 == 0 && inp1 == 4)
		begin
			out <= 5;
		end
		else if (inp0 == 1 && inp1 == 4)
		begin
			out <= 6;
		end
		else if (inp0 == 1 && inp1 == 2)
		begin
			out <= 7;
		end
		else if (inp0 == 1 && inp1 == 3)
		begin
			out <= 8;
		end
		else if (inp0 == 0 && inp1 == 1)
		begin
			out <= 9;
		end
		else if (inp0 == 1 && inp1 == 0)
		begin
			out <= 10;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_11(inp, out0, out1);
	input [3:0] inp;
	output reg [1:0] out0;
	output reg [2:0] out1;
	always @ (inp)
	begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		2:
		begin
			out0 <= 1;
			out1 <= 1;
		end
		3:
		begin
			out0 <= 0;
			out1 <= 3;
		end
		4:
		begin
			out0 <= 0;
			out1 <= 2;
		end
		5:
		begin
			out0 <= 0;
			out1 <= 4;
		end
		6:
		begin
			out0 <= 1;
			out1 <= 4;
		end
		7:
		begin
			out0 <= 1;
			out1 <= 2;
		end
		8:
		begin
			out0 <= 1;
			out1 <= 3;
		end
		9:
		begin
			out0 <= 0;
			out1 <= 1;
		end
		10:
		begin
			out0 <= 1;
			out1 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
		end
		endcase
	end
endmodule

module atop_testbench();
	reg [3:0] inp1;
	reg [3:0] inp2;
	wire [3:0] out;

integer i, j, l, m, k, t;
	reg dummy;
	integer fori, forj;
	multiplication_mod_11 mul1(inp1, inp2, out);
	initial
	begin
	k = 1;
	for (fori = 0; fori < 11; fori = fori + 1)
	begin
	for (forj = 0; forj < 11; forj = forj + 1)
	begin
		inp1 = fori;
		inp2 = forj;
		#1 dummy = 1;
		i = (fori*forj)%11;
		$display ("!!! OP1 = (%d) OP2 = (%d) RES = (%d) EXPECT = (%d)", fori, forj, out, i);
		l = out;
		if (l != i)
		begin
			$display ("!!! Error (%d, %d)!!!", i, l);
		end
		#1 dummy = 1;
	end
	end
	end
endmodule

	1	0 0
	2	1 1
	3	0 3
	4	0 2
	5	0 4
	6	1 4
	7	1 2
	8	1 3
	9	0 1
	10	1 0

Сумматор
по
модулю 2

(0 + 1) mod 2 = 1

Сумматор
по
модулю 5

(0 + 1) mod 5 = 1

0 0	1
0 1	9
0 2	4
0 3	3
0 4	5
1 0	10
1 1	2
1 2	7
1 3	8
1 4	6

	1	0 0
	2	1 1
	3	0 3
	4	0 2
	5	0 4
	6	1 4
	7	1 2
	8	1 3
	9	0 1
	10	1 0

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