Генератор Verilog для индексных умножителей по модулю (Модуль: 31)

Генератор Verilog для индексных умножителей по модулю

Первообразный корень для 31 = 3
Число P-1 может быть разложено на 3 взаимнопростых множителя: 30 = 2*3*5

module multiplication_mod_31(inp1, inp2, out);
	input [4:0] inp1;
	input [4:0] inp2;
	output reg [4:0] out;
	wire [4:0] out_pre;
	wire [1:0] w_1_0;
	wire [1:0] w_2_0;
	wire [1:0] wout_0;
	wire [1:0] w_1_1;
	wire [1:0] w_2_1;
	wire [1:0] wout_1;
	wire [2:0] w_1_2;
	wire [2:0] w_2_2;
	wire [2:0] wout_2;
	lut_input_31 lut1(inp1, w_1_0, w_1_1, w_1_2);
	lut_input_31 lut2(inp2, w_2_0, w_2_1, w_2_2);
	sum_modulo_2 sm0(w_1_0, w_2_0, wout_0);
	sum_modulo_3 sm1(w_1_1, w_2_1, wout_1);
	sum_modulo_5 sm2(w_1_2, w_2_2, wout_2);
	lut_output_31 lut3(wout_0, wout_1, wout_2, out_pre);
	always @ (*)
	begin
		if (inp1 == 0 || inp2 == 0)
		begin
			out = 0;
		end
		else
		begin
			out = out_pre;
		end
	end
endmodule

module sum_modulo_2(inp1, inp2, out);
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 2)
		begin
			out = int;
		end
		else
		begin
			out = int - 2;
		end
	end
endmodule

module sum_modulo_3(inp1, inp2, out);
	input [1:0] inp1;
	input [1:0] inp2;
	output reg [1:0] out;
	wire [2:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 3)
		begin
			out = int;
		end
		else
		begin
			out = int - 3;
		end
	end
endmodule

module sum_modulo_5(inp1, inp2, out);
	input [2:0] inp1;
	input [2:0] inp2;
	output reg [2:0] out;
	wire [3:0] int;
	assign int = inp1 + inp2;
	always @ (*)
	begin
		if (int < 5)
		begin
			out = int;
		end
		else
		begin
			out = int - 5;
		end
	end
endmodule

module lut_output_31(inp0, inp1, inp2, out);
	output reg [4:0] out;
	input [1:0] inp0;
	input [1:0] inp1;
	input [2:0] inp2;
	always @ (*)
	begin
		if (inp0 == 0 && inp1 == 0 && inp2 == 0)
		begin
			out <= 1;
		end
		else if (inp0 == 0 && inp1 == 0 && inp2 == 4)
		begin
			out <= 2;
		end
		else if (inp0 == 1 && inp1 == 1 && inp2 == 1)
		begin
			out <= 3;
		end
		else if (inp0 == 0 && inp1 == 0 && inp2 == 3)
		begin
			out <= 4;
		end
		else if (inp0 == 0 && inp1 == 2 && inp2 == 0)
		begin
			out <= 5;
		end
		else if (inp0 == 1 && inp1 == 1 && inp2 == 0)
		begin
			out <= 6;
		end
		else if (inp0 == 0 && inp1 == 1 && inp2 == 3)
		begin
			out <= 7;
		end
		else if (inp0 == 0 && inp1 == 0 && inp2 == 2)
		begin
			out <= 8;
		end
		else if (inp0 == 0 && inp1 == 2 && inp2 == 2)
		begin
			out <= 9;
		end
		else if (inp0 == 0 && inp1 == 2 && inp2 == 4)
		begin
			out <= 10;
		end
		else if (inp0 == 1 && inp1 == 2 && inp2 == 3)
		begin
			out <= 11;
		end
		else if (inp0 == 1 && inp1 == 1 && inp2 == 4)
		begin
			out <= 12;
		end
		else if (inp0 == 1 && inp1 == 2 && inp2 == 1)
		begin
			out <= 13;
		end
		else if (inp0 == 0 && inp1 == 1 && inp2 == 2)
		begin
			out <= 14;
		end
		else if (inp0 == 1 && inp1 == 0 && inp2 == 1)
		begin
			out <= 15;
		end
		else if (inp0 == 0 && inp1 == 0 && inp2 == 1)
		begin
			out <= 16;
		end
		else if (inp0 == 1 && inp1 == 1 && inp2 == 2)
		begin
			out <= 17;
		end
		else if (inp0 == 0 && inp1 == 2 && inp2 == 1)
		begin
			out <= 18;
		end
		else if (inp0 == 0 && inp1 == 1 && inp2 == 4)
		begin
			out <= 19;
		end
		else if (inp0 == 0 && inp1 == 2 && inp2 == 3)
		begin
			out <= 20;
		end
		else if (inp0 == 1 && inp1 == 2 && inp2 == 4)
		begin
			out <= 21;
		end
		else if (inp0 == 1 && inp1 == 2 && inp2 == 2)
		begin
			out <= 22;
		end
		else if (inp0 == 1 && inp1 == 0 && inp2 == 2)
		begin
			out <= 23;
		end
		else if (inp0 == 1 && inp1 == 1 && inp2 == 3)
		begin
			out <= 24;
		end
		else if (inp0 == 0 && inp1 == 1 && inp2 == 0)
		begin
			out <= 25;
		end
		else if (inp0 == 1 && inp1 == 2 && inp2 == 0)
		begin
			out <= 26;
		end
		else if (inp0 == 1 && inp1 == 0 && inp2 == 3)
		begin
			out <= 27;
		end
		else if (inp0 == 0 && inp1 == 1 && inp2 == 1)
		begin
			out <= 28;
		end
		else if (inp0 == 1 && inp1 == 0 && inp2 == 4)
		begin
			out <= 29;
		end
		else if (inp0 == 1 && inp1 == 0 && inp2 == 0)
		begin
			out <= 30;
		end
		else 
		begin
			out <= 0;
		end
	end
endmodule

module lut_input_31(inp, out0, out1, out2);
	input [4:0] inp;
	output reg [1:0] out0;
	output reg [1:0] out1;
	output reg [2:0] out2;
	always @ (inp)
	begin
		case(inp)
		1:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 0;
		end
		2:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 4;
		end
		3:
		begin
			out0 <= 1;
			out1 <= 1;
			out2 <= 1;
		end
		4:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 3;
		end
		5:
		begin
			out0 <= 0;
			out1 <= 2;
			out2 <= 0;
		end
		6:
		begin
			out0 <= 1;
			out1 <= 1;
			out2 <= 0;
		end
		7:
		begin
			out0 <= 0;
			out1 <= 1;
			out2 <= 3;
		end
		8:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 2;
		end
		9:
		begin
			out0 <= 0;
			out1 <= 2;
			out2 <= 2;
		end
		10:
		begin
			out0 <= 0;
			out1 <= 2;
			out2 <= 4;
		end
		11:
		begin
			out0 <= 1;
			out1 <= 2;
			out2 <= 3;
		end
		12:
		begin
			out0 <= 1;
			out1 <= 1;
			out2 <= 4;
		end
		13:
		begin
			out0 <= 1;
			out1 <= 2;
			out2 <= 1;
		end
		14:
		begin
			out0 <= 0;
			out1 <= 1;
			out2 <= 2;
		end
		15:
		begin
			out0 <= 1;
			out1 <= 0;
			out2 <= 1;
		end
		16:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 1;
		end
		17:
		begin
			out0 <= 1;
			out1 <= 1;
			out2 <= 2;
		end
		18:
		begin
			out0 <= 0;
			out1 <= 2;
			out2 <= 1;
		end
		19:
		begin
			out0 <= 0;
			out1 <= 1;
			out2 <= 4;
		end
		20:
		begin
			out0 <= 0;
			out1 <= 2;
			out2 <= 3;
		end
		21:
		begin
			out0 <= 1;
			out1 <= 2;
			out2 <= 4;
		end
		22:
		begin
			out0 <= 1;
			out1 <= 2;
			out2 <= 2;
		end
		23:
		begin
			out0 <= 1;
			out1 <= 0;
			out2 <= 2;
		end
		24:
		begin
			out0 <= 1;
			out1 <= 1;
			out2 <= 3;
		end
		25:
		begin
			out0 <= 0;
			out1 <= 1;
			out2 <= 0;
		end
		26:
		begin
			out0 <= 1;
			out1 <= 2;
			out2 <= 0;
		end
		27:
		begin
			out0 <= 1;
			out1 <= 0;
			out2 <= 3;
		end
		28:
		begin
			out0 <= 0;
			out1 <= 1;
			out2 <= 1;
		end
		29:
		begin
			out0 <= 1;
			out1 <= 0;
			out2 <= 4;
		end
		30:
		begin
			out0 <= 1;
			out1 <= 0;
			out2 <= 0;
		end
		default:
		begin
			out0 <= 0;
			out1 <= 0;
			out2 <= 0;
		end
		endcase
	end
endmodule

module atop_testbench();
	reg [4:0] inp1;
	reg [4:0] inp2;
	wire [4:0] out;

integer i, j, l, m, k, t;
	reg dummy;
	integer fori, forj;
	multiplication_mod_31 mul1(inp1, inp2, out);
	initial
	begin
	k = 1;
	for (fori = 0; fori < 31; fori = fori + 1)
	begin
	for (forj = 0; forj < 31; forj = forj + 1)
	begin
		inp1 = fori;
		inp2 = forj;
		#1 dummy = 1;
		i = (fori*forj)%31;
		$display ("!!! OP1 = (%d) OP2 = (%d) RES = (%d) EXPECT = (%d)", fori, forj, out, i);
		l = out;
		if (l != i)
		begin
			$display ("!!! Error (%d, %d)!!!", i, l);
		end
		#1 dummy = 1;
	end
	end
	end
endmodule

	1	0 0 0
	2	0 0 4
	3	1 1 1
	4	0 0 3
	5	0 2 0
	6	1 1 0
	7	0 1 3
	8	0 0 2
	9	0 2 2
	10	0 2 4
	11	1 2 3
	12	1 1 4
	13	1 2 1
	14	0 1 2
	15	1 0 1
	16	0 0 1
	17	1 1 2
	18	0 2 1
	19	0 1 4
	20	0 2 3
	21	1 2 4
	22	1 2 2
	23	1 0 2
	24	1 1 3
	25	0 1 0
	26	1 2 0
	27	1 0 3
	28	0 1 1
	29	1 0 4
	30	1 0 0

Сумматор
по
модулю 2

(0 + 0) mod 2 = 0

Сумматор
по
модулю 3

(0 + 2) mod 3 = 2

Сумматор
по
модулю 5

(3 + 3) mod 5 = 1

0 0 0	1
0 0 1	16
0 0 2	8
0 0 3	4
0 0 4	2
0 1 0	25
0 1 1	28
0 1 2	14
0 1 3	7
0 1 4	19
0 2 0	5
0 2 1	18
0 2 2	9
0 2 3	20
0 2 4	10
1 0 0	30
1 0 1	15
1 0 2	23
1 0 3	27
1 0 4	29
1 1 0	6
1 1 1	3
1 1 2	17
1 1 3	24
1 1 4	12
1 2 0	26
1 2 1	13
1 2 2	22
1 2 3	11
1 2 4	21

	1	0 0 0
	2	0 0 4
	3	1 1 1
	4	0 0 3
	5	0 2 0
	6	1 1 0
	7	0 1 3
	8	0 0 2
	9	0 2 2
	10	0 2 4
	11	1 2 3
	12	1 1 4
	13	1 2 1
	14	0 1 2
	15	1 0 1
	16	0 0 1
	17	1 1 2
	18	0 2 1
	19	0 1 4
	20	0 2 3
	21	1 2 4
	22	1 2 2
	23	1 0 2
	24	1 1 3
	25	0 1 0
	26	1 2 0
	27	1 0 3
	28	0 1 1
	29	1 0 4
	30	1 0 0

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